Computer systems are generally designed with certain cost and performance objectives. Increased performance with minimum increased cost is always desirable but not always achieved. Control storages and data paths can be increased in width to provide improved performance but that is a relatively expensive solution. On the other hand, cost and performance degrades when the number of control words required to perform additional functions increase. The additional control words are costly in terms of control storage costs, manpower costs for coding the control words and maintenance costs. The requirement of executing a sequence of control words to perform a function obviously is less efficient and slower than executing a single control word to do the same function.
The prior art, in an article in the IRE Transactions On Electronic Computers, June 1962, page 416, entitled "A Method of Increasing the Number of Orders in a Digital Computer", describes a technique of taking bits from one field such as an address field to extend or increase the number of orders which can be specified by the operation code. Not only is this technique entirely different from the present invention, it has certain penalties or disadvantages as pointed out in the article, i.e., a corresponding loss of storage addresses and increased hardware.
The present invention has substantially no loss of function or increase in hardware. This is because bits from one field are not used to increase the size of another field. Rather, some independent decodes from one field are used together with decodes from another field to specify multiples or pairs of dependent decodes. Hence, independent decodes from both fields still exist but the number thereof is reduced. The total number of decodes; however, is increased and the dependent decodes can specify functions of the sacrificed independent decodes and additionally can specify new functions.
The hardware is not substantially increased because the logic circuitry used for non-extended decoding can be used by the present invention. The additional requirement of the present invention is that the logic circuits have more than two inputs and it is not uncommon for control word decode circuitry to be implemented with logic circuits having more inputs than are being used. Also the inhibit function required by the present invention does not require any additional circuitry because both up and down level decodes are available and discrete inverters are not necessary although shown in the drawings to reduce the number of lines.
Thus the present invention increases performance because more functions can be performed during execution of a single control word. Further, since the size of the control word is not increased the costs of the improved performance provided by the present invention is incremental.